Datasheet

SN65LVCP408
www.ti.com SLLS842A –JUNE 2009–REVISED JUNE 2010
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
MULTIPLEXER
t
(SM)
Multiplexer switch time Multiplexer to valid output 15 ns
DIFFERENTIAL OUTPUTS
Low-to-high propagation
t
PLH
0.5 0.7 ns
delay
Propagation delay input to output, See Figure 6
High-to-low propagation
t
PHL
0.5 0.7 ns
delay
t
r
Rise time 90 ps
20% to 80% of V
O(DB)
; Test Pattern: 100-MHz clock signal;
See Figure 5 and Figure 8
t
f
Fall time 90 ps
t
sk(p)
Pulse skew, | t
PHL
– t
PLH
|
(2)
20 ps
t
sk(o)
Output skew
(3)
All outputs terminated with 100 Ω 25 75 ps
t
sk(pp)
Part-to-part skew
(4)
150 ps
3-State switch time to Assumes 50 Ω to Vcm and 150 pF load on each output;
t
zd
30 ns
Disable Tested using I2C
3-State switch time to Assumes 50 Ω to Vcm and 150 pF load on each output;
t
ze
20 ns
Enable Tested using I2C
See Figure 8 for test circuit. BERT setting 10
–15
RJ Device random jitter, rms 0.8 2 ps-rms
Alternating 10-pattern.
0 dB preemphasis
Intrinsic deterministic device PRBS 2
7-1
See Figure 8 for the test 4.25 Gbps 30 ps
jitter
(5)
, peak-to-peak pattern
circuit.
1.25Gbps;
EQ=13dB
15
Over 25-inch
DJ
FR4 trace
0 dB preemphasis
Absolute deterministic PRBS 2
7-1
See Figure 8 for the test ps
4.25 Gbps;
output jitter
(6)
, peak-to-peak pattern
circuit.
EQ=13dB
Over FR4 trace 40
2-inch to 43
inches long
(1) All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.
(3) t
sk(o)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any two outputs of a single device.
(4) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(5) The SN65LVCP408 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the
LVCP408 typically reduces jitter by 29 ps from the device input to the device output.
(6) Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP408 output. The value is a real measured
value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ
(absolute)
= DJ
(Signal generator)
+ DJ
(transmission line)
+ DJ
(intrinsic(LVCP408))
.
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