Datasheet

SN65LVCP408
www.ti.com SLLS842A –JUNE 2009–REVISED JUNE 2010
PIN FUNCTIONS
Pin
TYPE DESCRIPTION
NAME NO.
High Speed I/O
xA 5, 8, 11, 14, 18, 21, 24 ,27 Differential Inputs (with
50-Ω termination to Vbb) Line Side Differential Inputs CML compatible
xB 6, 9, 12, 15, 19, 22, 25, 28
xA=P; xB=N
xY 34, 37, 40 43, 51, 54, 57, 60
Differential Output xY=P;
Switch Side Differential Outputs. VML
xZ=N
xZ 33, 36, 39, 42, 50, 53, 56, 59
Control Signals
SCL 45
SDA 46
I
2
C Control Interface (SCL: Clock, SDA: Data, ADDR:
Inputs
Address)
ADDR1 47
ADDR2 48
Equalization setting when I
2
C is not enabled. EQ=0 for 13dB
EQ 31 Input
and setting EQ=1 for 9dB.
Pre-Emphasis setting when I
2
C is not enabled. PRE=0 for 0
PRE 32 Input
dB and PRE=1 for 6 dB
Enables I
2
C control interface I
2
C_EN=1 for enable; When
EN=0 then the PRE and EQ pins are used to set the
I2C_EN 63 Input Pre-Emphasis and Equalization settings rather than the I2C
register map. When EN=0 the I
2
C register map is still open
for read and write operations.
SWT 62 Input Enable switch event when toggled
Configuration Reset. Resets I
2
C register space (Active Low).
RESN 3 Input (Active Low) Note upon device startup the RESN pin must be driven low
to reset the device registers.
Power Supply
2, 7, 13, 20, 26, 30, 35, 41, 52,
VCC Power Power Supply 3.3v±5%
58, 64
1,4, 10, 17, 23, 29 , 38, 44, 49,
GND Ground
55, 61
V
BB
16 Input Receiver input biasing voltage
The ground center pad of the package must be connected to
PowerPAD™ Ground
GND plane.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65LVCP408