Datasheet

0Y
0Z
7Y
7Z
Registers
R
T
R
T
V
BB
R
T
R
T
0B
0A
2x1
MUX
24
24
24
SWT
I 2C
IF
ADDR1
ADDR2
SCL
SDA
RESN
I2C_EN
EQ
EQ
7A
7B
EQ
EQ
8x8
MUX
8x1
MUX
3
8x1
MUX
3
PRE
2
3-State_0
3-State_7
PRE
2
V
BB
SN65LVCP408
SLLS842A –JUNE 2009 –REVISED JUNE 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
LOGIC DIAGRAM
A. V
BB
: Receiver input internal biasing voltage (allows ac coupling)
B. R
T
: Internal 50-Ω receiver termination (100-Ω differential)
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