Datasheet

A =Not Acknowledge(SDA High)
A = Acknowledge(SDA Low)
S=StartCondition
P =StopCondition
=Write(SDA Low)
R=Read(SDA High)
W
FromSlave
RepeatnTimes
S Slave Address
R
A
RegisterData
A/A
P
FromMaster
A =Not Acknowledge(SDA High)
A = Acknowledge(SDA Low)
S=StartCondition
P =StopCondition
=Write(SDA Low)
R=Read(SDA High)
W
FromSlave
RepeatnTimes
FromMaster
S Slave Address
W
A Register Address AS Slave Address R Register Data
A/A
PA
SN65LVCP408
www.ti.com SLLS842A –JUNE 2009–REVISED JUNE 2010
Figure 25. I
2
C Read Cycle
Figure 26. I
2
C Combined Format Write/Read Cycle
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should
comply with the I
2
C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
slave address is the first 7 bits received following the START condition from the master device. The first 5 Bits
(MSBs) of the address are factory preset to 01011. The next two bits of the SN65LVCP408 address are
controlled by the logic levels appearing on the ADDR2 and ADDR1 pins. The ADDR2 and ADDR1 address inputs
can be connected to VCC for logic 1, GND for logic 0, or can be actively driven by TTL/CMOS logic levels. The
device addresses are set by the state of these pins and are not latched. Thus a dynamic address control system
could be utilized to incorporate several devices on the same system. Up to four SN65LVCP408 devices can be
connected to the same I
2
C-Bus without requiring additional glue logic. Table 2 lists the possible addresses for the
SN65LVCP408.
Table 2. Slave Addresses
Fixed Address Selectable with Address Pins
Bit 6 (MSB) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(addr2) Bit 0 (addr1)
0 1 0 1 1 0 0
0 1 0 1 1 0 1
0 1 0 1 1 1 0
0 1 0 1 1 1 1
Note: Following power up, this device must be reset.
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Product Folder Link(s): SN65LVCP408