Datasheet

handbook,fullpagewidth
S
1 – 7 8 9 1 – 7 8 9 1 – 7 8 9
P
STOP
condition
START
condition
DATA ACKDATA ACKADDRESS ACKR/W
SDA
SCL
A =Not Acknowledge(SDA High)
A = Acknowledge(SDA Low)
S=StartCondition
P =StopCondition
=Write(SDA Low)
R=Read(SDA High)
W
FromSlave
RepeatnTimes
S Slave Address
W
A
Register Address
A
Register Data
A
P
FromMaster
A =Not Acknowledge(SDA High)
A = Acknowledge(SDA Low)
S=StartCondition
P =StopCondition
=Write(SDA Low)
R=Read(SDA High)
W
FromSlave
S Slave Address
W
A
Register Address
FromMaster
A P
SN65LVCP408
SLLS842A –JUNE 2009 –REVISED JUNE 2010 www.ti.com
Figure 22. I
2
C Address and Data Cycles
During a write cycle, the slave sends an acknowledge (A) after every byte that follows the device address. The
first byte following the device address is the register address, which maps to the register addresses specific to
the device. The second byte following the device address is the data byte to be written at the register address
(see Figure 23). If only the register address is to be written for a subsequent read sequence, the data byte is
omitted and the sequence ends with a Stop (see Figure 24) or a repeated Start after the register address byte
(see Figure 26). If multiple data bytes are to be written at subsequent register addresses, the master may
continue to send data bytes after each slave acknowledge, and the slave device automatically increments the
register address. Note that the master must not drive the SDA signal line during the slave acknowledge since the
slave is in control of the SDA bus and may be holding it low.
During a read cycle, the slave acknowledges the initial address byte if it decodes the device address as its own
device address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. The first byte received by the master is the data stored at the
register address, while subsequent bytes are data stored at incrementing register addresses. When the master
has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the
master by keeping the SDA signal high just before it asserts the Stop (P) condition. This sequence terminates a
read cycle as shown in Figure 25. A combined format is when the read cycle is preceded by a write cycle for
setting the register address, and is shown in Figure 26.
Figure 23. I
2
C Write Cycle with Register Address and Data
Figure 24. I
2
C Write Cycle with Register Address Only
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