Datasheet

SCL
SDA
DataLine
Stable;
DataValid
ChangeofData Allowed
Start
Condition
ClockPulsefor
Acknowledgement
Acknowledge
Not Acknowledge
DataOutput
byReceiver
DataOutput
byTransmitter
SCL From
Master
S
1 2
8 9
SN65LVCP408
www.ti.com SLLS842A –JUNE 2009–REVISED JUNE 2010
Table 1. I
2
C Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
SCL clock frequency for internal register Local I
2
C 100 kHz
t
W(L)
Clock LOW period for I
2
C register Local I
2
C 4.7 ms
t
W(H)
Clock HIGH period for internal register Local I
2
C 4 ms
t
SU1
Internal register setup time, SDA to SCL Local I
2
C 250 ms
t
h(1)
Internal register hold time, SCL to SDA Local I
2
C 0 ms
Internal register bus free time between STOP
t
(buf)
Local I
2
C 4.7 ms
and START
t
su(2)
Internal register setup time, SCL to START Local I
2
C 4.7 ms
t
h(2)
Internal register hold time, START to SCL Local I
2
C 4 ms
t
su(3)
Internal register hold time, SCL to STOP Local I
2
C 4 ms
Figure 20. I
2
C Bit Transfer
Figure 21. I
2
C Acknowledge
Note: Following power up, this device must be reset.
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