Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Switch Crosspoint switch Single supply HTQFP 64 (10x10)

SDA

ADDR2

ADDR1

GND

VCC

SCL

VCC

GND

VCC

GND

PRE

VCC

GND

VCC

I2C_EN

SWT

VCC

GND

VCC

GND

RESN

VCC

GND

VBB

GND

VCC

61 606264 63 5658 57 5355 54 4952 51 50

2220 211917 18 2523 24 2826 27 3229 30 31

SN65LVCP408

www.ti.com

SLLS842A –JUNE 2009–REVISED JUNE 2010

Gigabit 8 x 8 CROSSPOINT SWITCH

Check for Samples: SN65LVCP408

FEATURES

DESCRIPTION

• Up to 4.25 Gbps Operation

The SN65LVCP408 is a 8 × 8 non-blocking

crosspoint switch in a flow-through pin-out allowing

• Non-Blocking Architecture Allows Each

for ease in PCB layout. VML signaling is used to

Output to be Connected to Any Input

achieve a high-speed data throughput while using low

• 30 ps of Deterministic Jitter

power. Each of the output drivers includes a 8:1

• Selectable Transmit Pre-Emphasis Per Lane

multiplexer to allow any input to be routed to any

output. Internal signal paths are fully differential to

• Selectable Receive Equalization

achieve the high signaling speeds while maintaining

• Available Packaging 64 Pin QFP

low signal skews. The SN65LVCP408 incorporates

• Propagation Delay Times: 500 ps Typical

100-Ω termination resistors for those applications

where board space is a premium. Built-in transmit

• Inputs Electrically Compatible With

pre-emphasis and receive equalization for superior

CML Signal Levels

signal integrity performance.

• Operates From a Single 3.3-V Supply

The SN65LVCP408 is characterized for operation

• Ability to 3-STATE Outputs

from –40°C to 85°C. (See operating free air condition

• Integrated Termination Resistors

requirements)

• I

C™ Control Interface

APPLICATIONS

• Clock Buffering/Clock MUXing

• Wireless Base Stations

• High-Speed Network Routing

• Telecom/Datacom

• XAUI 802.3ae Protocol Backplane Redundancy

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 Gigabit 8 x 8 CROSSPOINT SWITCH Check for Samples: SN65LVCP408 FEATURES DESCRIPTION • • The SN65LVCP408 is a 8 × 8 non-blocking crosspoint switch in a flow-through pin-out allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 8:1 multiplexer to allow any input to be routed to any output.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 PIN FUNCTIONS Pin NAME NO. TYPE DESCRIPTION Differential Inputs (with 50-Ω termination to Vbb) xA=P; xB=N Line Side Differential Inputs CML compatible Differential Output xY=P; xZ=N Switch Side Differential Outputs.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W Gain Stage + EQ VCC RBBDC RT(SE) = 50 W IN− VBB ESD LineEndTermination Self−Biasing Network Figure 1. Equivalent Input Circuit Design OUT+ 49.9 W OUT− 49.9 W VOCM 1 pF Figure 2.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage range (2) –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ Receiver inputs Human Body Model (3) Charged-Device Model –0.5 V to (VCC + 0.5 V) –0.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT MULTIPLEXER t(SM) Multiplexer switch time Multiplexer to valid output 15 ns 0.5 0.7 ns 0.5 0.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VODPE3(pp) 10−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 3. Preemphasis and Output Voltage Waveforms and Definitions 1−bit VODPE3(pp) 10−dB Preemphasis 1 to N bit VODB(PP) 80% 20% tPRE Figure 4. t(PRE) Preemphasis Duration Measurement 80% 80% VODB 20% 20% tr tf Figure 5.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 PARAMETER MEASUREMENT INFORMATION (continued) VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 6.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com TYPICAL DEVICE BEHAVIOR Eye After 43-inch FR-4 Trace, Input 400 mVPP Eye After 43-inch FR-4 Trace, Input 400 mVPP, Through the 408 With Pre-emphasis at 3 dB 0 0 0 1 0dB 3dB 1 1 0 1 6dB 10dB 100 ps/div Pre-emphasis Levels Figure 10. Preemphasis Signal Shape 50 ps/div Figure 9. Data Input and Output Pattern 4.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 Figure 12. SN65LVCP408 Passing 3G (2.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com Figure 13. SN65LVCP408 Passing 3G (2.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS DETERMINISTIC OUTPUT JITTER vs DATA RATE DETERMINISTIC OUTPUT JITTER vs DIFFERENTIAL INPUT AMPLITUDE 50 60 1400 4.25 Gbps 45 50 40 30 20 10 1200 2.5 Gbps 40 1000 3.125 Gbps 35 30 VOD - Differential Output Voltage - VPP 27-1 PRBS pattern, The DJ is Measured on the Output of the LVCP408 Deterministic Output jitter - ps Deterministic Output Jitter - ps 70 3.75 Gbps 25 1.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com I2C CONTROL INTERFACE I2C Interface Notes The I2C interface is used to access the internal registers of the SN65LVCP408. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 Table 1. I2C Timing PARAMETER fSCL TEST CONDITIONS MIN TYP Local I2C SCL clock frequency for internal register 2 2 MAX UNIT 100 kHz tW(L) Clock LOW period for I C register Local I C 4.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com handbook, full pagewidth SDA SCL 1–7 8 9 1–7 8 9 1–7 8 9 P S START ADDRESS condition R/W ACK DATA ACK DATA ACK STOP condition Figure 22. I2C Address and Data Cycles During a write cycle, the slave sends an acknowledge (A) after every byte that follows the device address. The first byte following the device address is the register address, which maps to the register addresses specific to the device.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 Repeat n Times S Slave Address R Register Data A A/A A = Not Acknowledge (SDA High) A = Acknowledge (SDA Low) S = Start Condition P = Stop Condition W = Write (SDA Low) R = Read (SDA High) P From Master From Slave Figure 25.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com Table 3.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 Table 6. Switch Control Bit 7 Function Enable Switch Via Pin Default Note 0 0= Switch Via I2C bit is used to enable the switch event; 1 = Switch via SWT pin; When SWT is logic 0, Port Select No. 1 settings will be used. When SWT is logic 1, the Port Select No. 2 settings will be used. The Switch Via i2C setting will be ignored. 6 Switch Via I2C 0 Selects between Port Select No. 1 and No. 2 when enable Switch Via Pin is 0.
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SN65LVCP408 SLLS842A – JUNE 2009 – REVISED JUNE 2010 www.ti.com Signal Amplitude − dB 0 20 dB/dec 1875 MHz With 80 ps Rise Time −5 20 dB/dec 375 MHz With 80 ps Rise Time −10 40 dB/dec −15 80% 20% tr −20 −25 40 dB/dec tPeriod = 1/f 100 1000 f − Frequency − MHz 1/(pi x 100/60 tr) = 2.4 GHz 10000 Figure 27.
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SN65LVCP408 www.ti.com SLLS842A – JUNE 2009 – REVISED JUNE 2010 REVISION HISTORY Changes from Original (June 2009) to Revision A • Page Added Figures 12 (Figure 11a) and Figure 13 (Figure 11b) ...............................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVCP408PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 SN65LVCP408PAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVCP408PAPR HTQFP PAP 64 1000 367.0 367.0 45.0 SN65LVCP408PAPT HTQFP PAP 64 250 367.0 367.0 45.
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