Datasheet

Overview
2-2
2.1 Overview
The output characteristics of the SN65LVCP23 (LVPECL) drivers are
generally loaded with 50-Ω resistors to a termination bias voltage, V
TT
. V
TT
is
usually 2 V below the supply voltage of the driver circuit. When the driver
operates from a 3.3-V supply, V
TT
is set to approximately 1.3 V.
The output characteristics of the SN65LVCP22 are specified in the
TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential
signal, with a 1.25–V offset from ground. These levels are attained when
driving a 100-W differential line-termination test load. This requirement
includes the effects of up to 32 standard receivers with their ground reference
up to 1 V different from that of the driver. This common-mode loading limitation
of LVDS drivers affects how they are observed and much of the test setup that
follows..
The EVM is designed to support the SN65LVCP22 LVDS output device as well
as the SN65LVCP23 LVPECL output device. By using the three power jacks
(J17, J18, J19), as well as installing termination resistors (R3–R8 and
R11–R16), different methods of termination and probing can be used to
evaluate the device output characteristics. The typical setup for the
SN65LVCP22 is shown in Figure 2–1.
Figure 2–1. EVM Power Connections for SN65LVCP22/23 Evaluation—With LVDS Inputs
50 Ω
SN65LVCP22/23 EVM
+
–
+
–
CH1
CH2
CH3
CH4
Oscilloscope
VCC
J17J18J19
J8 or J16
J7 or J15
J6 or J14
J5 or J13
J2 or J10
J3 or J11
J4 or J12
Power Supply #1 3.3 V
Power Supply #2 1.2 V
Pattern
Generator
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
J1 or J9
VCC01
(DUT GND)
GND
(EVM GND)
R1 or R19
100 Ω
R2 or R10
100 Ω
50 Ω
50 Ω
50 Ω