User’s Guide June 2003 HPL Interface SLLU060
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range between 1.2 V and 3.3 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Trademarks Preface About This Manual This user’s guide describes the SN65LVCP22/23 evaluation module (EVM). This guide contains the EVM schematic, bill of materials, assembly drawing, and board layouts. How to Use This Manual This document contains the following chapters: - Chapter 1– Introduction - Chapter 2– Setup and Equipment Required - Chapter 3– EVM Construction - Chapter 4– PCB Fabrication and Bill of Materials This user’s guide may contain cautions and warnings.
Trademarks Electrostatic Sensitive Devices This EVM contains components that can potentially be damaged by electrostatic discharge. Always transport and store the EVM in its supplied ESD bag when not in use. Handle using an antistatic wristband. Operate on an antistatic work surface. For more information on proper handling, refer to SSYA008.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Setup and Equipment Required . . . . .
Contents 1–1 1–2 1–3 2–1 2–2 2–3 3–1 3–2 3–3 3–4 3–5 3–6 3–7 Functional Configurations of the SN65LVCP22 and SN65LVCP23 . . . . . . . . . . . . . . . . . . . SN65LVCP22/23 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN65LVCP22/23 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EVM Power Connections for SN65LVCP22/23 Evaluation—With LVDS Inputs . . . . . . .
Chapter 1 The SN65LVCP22/23 EVM highlights the high-speed performance and functionality of the SN65LVCP22 and SN65LVCP23 2x2 crosspoint switches. Topic Page 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Signal Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview 1.1 Overview The SN65LVCP22 (LVDS output) and SN65LVCP23 (LVPECL output) are high-speed 2x2 crosspoint switches. The four different functions that these crosspoints provide are shown in Figure 1–1. The functions of these crosspoints are selected via pins SEL0 and SEL1. Control pins EN0 and EN1 enable or disable the outputs. The receiver has a wide input common-mode voltage range with an ability to accept LVDS, LVPECL and CML signaling levels. Figure 1–1.
Signal Paths 1.2 Signal Paths The signal paths on this EVM include 16 edge-launch SMA connectors (J1–J16) for high-speed data transmission, 4 jumpers (JMP1, JMP2 for DUT1and JMP5, JMP6 for DUT2) for active switch logic control, 4 jumpers (JMP3, JMP4 for DUT1and JMP7, JMP8 for DUT2) for enabling and disabling the outputs, and three banana jacks (J17, J18, J19) for power and ground connections. See Figure 1–3. J10 J11 J12 J1 DUTGND VCC01 R3 uninstalled R4 J5 GND 68µF 1µF 68µF 1µF 0.1µF 0.1µF 0.
1-4
Chapter 2 Topic Page 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Applying an Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Observing an Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Typical Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview 2.1 Overview The output characteristics of the SN65LVCP23 (LVPECL) drivers are generally loaded with 50-Ω resistors to a termination bias voltage, VTT. VTT is usually 2 V below the supply voltage of the driver circuit. When the driver operates from a 3.3-V supply, VTT is set to approximately 1.3 V. The output characteristics of the SN65LVCP22 are specified in the TIA/EIA-644 standard. LVDS drivers nominally provide a 350-mV differential signal, with a 1.25–V offset from ground.
Applying an Input 2.2 Applying an Input When using a general-purpose signal generator with 50-Ω output impedance, make sure that the signal levels are between 0-V and 4-V with respect to J19, device under test ground (DUT GND), designated as Vcc01. Inputs should be applied to the SMA connectors J1, J2, J3, and J4 for DUT1 (or J9, J10, J11 and J12 for DUT2).
Observing an Output Table 2–1. Crosspoint Function Table SEL0 SEL1 OUT0 OUT1 Function 0 0 IN0 IN0 1:2 Splitter 0 1 IN0 IN1 Repeater 1 0 IN1 IN0 Switch 1 1 IN1 IN1 1:2 Splitter 2.3 Observing an Output Direct connection to an oscilloscope with 50–Ω internal terminations to ground is accomplished without R3–R8 (DUT1) and R11–R16 (DUT2) installed. The outputs are available at J5–J8 (DUT1) and J13–J16 (DUT2) for direct connection to oscilloscope inputs.
Typical Test Results 2.4 Typical Test Results Figure 2–3 is a typical result obtained with the EVM setup shown in Figure 2–1. The upper waveform is the difference voltage between channels 1 and 2 of the oscilloscope and the lower trace is the difference voltage between channels 3 and 4. The DUT was configured to send the IN0+/IN0– inputs to the outputs OUT0+/OUT0– and inputs IN1+/IN1– to outputs OUT1+/OUT1– by setting EN0 and EN1 to a high level and by setting SEL0 to Gnd and SEL1 to Vcc.
Chapter 3 Topic Page 3.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Board Layout Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 J4 J3 J2 J1 VCC01 1 GND GND GND GND R1 100 Ω R2 100 Ω JMP1 3pin_berg 2 3 VCC VCC01 VCC VCC VCC 2 C11 .
J12 J11 J10 J9 VCC01 GND GND GND GND 1 2 JMP5 3pin_berg 3 100Ω R10 100Ω R19 VCC VCC01 1 3 8 GND SN65LVCP23D VCC OUT1– 7 IN1– GND OUT0– OUT0+ EN1 EN0 OUT1+ VCC IN0– IN0+ SEL0 SEL1 DUT2 VCC IN1+ 6 5 4 3 2 1 VCC C17 .
Board Layout Patterns 3.2 Board Layout Patterns Figure 3–3. SN65LVCP22/23 Silk Screen Figure 3–4.
Board Layout Patterns Figure 3–5. Layer 2 – GND Plane Figure 3–6.
Board Layout Patterns Figure 3–7.
Chapter 4 Topic Page 4.1 PCB Fabrication Notes and Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB Fabrication Notes and Stackup 4.1 PCB Fabrication Notes and Stackup Notes: 1) All fabrication items must meet or exceed best industry practice. IPC–A 600C (Commercial Std.) 2) Laminate material NELCO N4000–13 [DO NOT USE–13SI] 3) Copper weight: 1 oz start internal and 1/2 oz start external Stackup Signal: Layer 1 4) Finished board thickness: 0.62” ±0.10” 0.008” 5) Maximum warp and twist to be 0.005 inch per inch GND: Layer 2 6) Minimim copper wall thickness of plate-through holes 0.
