Datasheet

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Test Setup

Figure 2. SN65LVCP114 EVM Jumper Description

5 Test Setup

The SN65LVCP114 EVM gives the developer two control interface options for operation, I2C or GPIO

mode. Input and Output differential pairs are available through edge-launch SMAs with approximately 2.5

inches of trace with Rogers Low–Dielectric material with 0.1 µF AC Coupling capacitors. Power to the

device, VCC, is applied using banana jacks (P1, P2). The USB-to-I2C circuitry on the board uses power

from the USB 5-V signal.

Table 1. SN65LVCP114 EVM Pin and Jumper Functionality

Description

Ref Des Symbol

GPIO mode I2C mode

J1, J3 AINP2, AINN2 Differential input, lane 2, Fabric switch A side

J2, J4 AOUTP2, AOUTN2 Differential output, lane 2, Fabric switch A side

J5, J7 BINP2, BINN2 Differential input, lane 2, Fabric switch B side

J6, J8 BOUTP2, BOUTN2 Differential output, lane 2, Fabric switch B side

J9, J11 CINP2, CINN2 Differential input, lane 2, Fabric switch C side

J10, J12 COUTP2, COUTN2 Differential output, lane 2, Fabric switch C side

P1 VCC Banana jack, positive power supply connection

P2 GND Banana jack, ground power supply connection

J13 USB USB cable connection

High, acts as Chip Select

JMP2 CS Don't Care

Low, disables the I2C interface

High, normal operation

JMP5 PDZ

Low, powers down the device, inputs off and outputs disabled, resets the I2C

Configures the device in I2C or GPIO mode of operation

JMP1 I2C_SEL High, enables I2C mode

Low, enables GPIO mode

JMP8 I2C_A0_EQA1 3 level control for EQ gain of port A I2C Address

JMP6 I2C_A1_EQB1 3 level control for EQ gain of port B I2C Address

JMP16 EQ_C0 3 level control for EQ gain of port C Don't care

JMP3 I2C_A2_EQC1 3 level control for EQ gain of port C I2C Address

SLLU160–December 2011 SN65LVCP114 Evaluation Module (EVM)

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