Datasheet

R
I
Start
Bit
D
00
− D
09
SYMBOL N+2
Stop
Bit
1.2 V
1 V
Start
Bit
D
00
− D
09
SYMBOL N+1
Stop
Bit
Start
Bit
D
00
− D
09
SYMBOL N
Stop
Bit
R
OUT
t
DD
R
OUT0
− R
OUT9
SYMBOL N−1 R
OUT0
− R
OUT9
SYMBOL N
Timing for TCLK_R/F
= High
RCLK
R
OUT0
− R
OUT9
SYMBOL N+1
R
OUT
[9:0]
RCLK
RCLK_R/F = High
t
ROS
Data Valid
Before RCLK
1.5 V1.5 V
t
ROH
t
Low
t
High
RCLK
RCLK_R/F
= Low
t
High
t
Low
Data Valid
After RCLK
7 V x (LZ/ZL), Open (HZ/ZH)
REN
t
d(ZL)
t
d(LZ)
1.5 V1.5 V
V
OH
V
OL
V
OL
+ 0.5 V
V
OL
R
OUT
[9:0]
V
OH
t
d(ZH)
t
d(HZ)
500 Ω
450 Ω
50 Ω
Scope
V
OL
+ 0.5 V
V
OH
− 0.5 V
V
OH
− 0.5 V
SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
Figure 14. Deserializer Delay
Figure 15. Deserializer Data Valid Out Times
Figure 16. Deserializer High-Impedance State Test Circuit and Timing
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Product Folder Link(s): SN65LV1023A SN65LV1224B