Datasheet

D
IN
[9:0]
t
su(DI)
TCLK
t
h(DI)
For TCLK_R/F = Low
Setup Hold 1.5 V1.5 V
t
TCP
1.5 V 1.5 V 1.5 V
13.5 Ω
D
O
+
D
O
−
Parasitic Package and
Trace Capacitance
DEN
t
d(ZH)
t
d(HZ)
1.5 V1.5 V
3 V
0 V
50%50%
1.1 V
V
OH
D
O
±
V
OL
1.1 V
t
d(ZL)
50%
50%
t
d(LZ)
13.5 Ω
1.1 V
DEN
D
O
±
TCLK
t
d(HZ)
or t
d(LZ)
2 V
1026 Cycles
PWRDN
0.8 V
Output Active
t
PLD
t
d(ZH)
or t
d(ZL)
3-State 3-State
SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
Figure 9. Serializer Setup/Hold Times
Figure 10. Serializer High-Impedance State Test Circuit and Timing
Figure 11. Serializer PLL Lock Time and PWRDN High-Impedance State Delays
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