Datasheet
SN65LV1023A
SN65LV1224B
www.ti.com
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
DESERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST PIN/FREQ MIN TYP MAX UNIT
CONDITIONS
t
(RCP)
= t
(TCP)
, See
t
(RCP)
Receiver out clock period RCLK 15.15 100 ns
Figure 13
t
TLH(C)
CMOS/TTL low-to-high ROUT0−ROUT9
1.2 2.5
C
L
= 15 pF, CL =
transition time LOCK, RCLK
15 pF, See ns
t
THL(C)
CMOS/TTL high-to-low
Figure 7
1.1 2.5
transition time
1.75×t
(RCP)
1.75×t
(RCP)
10 MHz ns
+4.2 +12.6
Deserializer delay, See Room temperature,
t
d(D)
Figure 14 3.3 V
1.75×t
(RCP)
1.75×t
(RCP)
66 MHz ns
+7.4 +9.7
RCLK 10 MHz 0.4×t
(RCP)
0.5×t
(RCP)
t
(ROS)
R
OUTx
data valid before RCLK
RCLK 66 MHz 0.4×t
(RCP)
0.5×t
(RCP)
See Figure 15 ns
10 MHz −0.4×t
(RCP)
−0.5×t
(RCP)
t
(ROH)
R
OUTx
data valid after RCLK
66 MHz −0.4×t
(RCP)
−0.5×t
(RCP)
t
(RDC)
RCLK duty cycle 40% 50% 60% ns
t
d(HZ)
High-to-high impedance state 6.5 8 ns
delay
t
d(LZ)
Low-to-high impedance state 4.7 8 ns
delay
See Figure 16 R
OUT0
−R
OUT9
t
d(HR)
High-impedance state to high 5.3 8 ns
delay
t
d(ZL)
High-impedance state to low 4.7 8 ns
delay
10 MHz 850 x t
RFCP
Deserializer PLL lock time from
t
(DSR1)
66 MHz 850 x t
RFCP
PWRDN (with SYNCPAT)
μs
See Figure 17,
10 MHz 2
Figure 18,
Deserializer PLL lock time from
t
(DSR2)
66 MHz 0.303
and
(1)
SYNCPAT
High-impedance state to high
t
d(ZHLK)
LOCK 3 ns
delay (power up)
10 MHz 3680
See Figure 19 and
t
RNM
Deserializer noise margin ps
(2)
66 MHz 540
(1) t
(DSR1)
represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the
powerdown mode. t
(DSR2)
represents the time required to register that a lock has occurred for the powered up and enabled deserializer
when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify
deserializer PLL performance, t
DSR1
and t
DSR2
are specified with REFCLK active and stable and specific conditions of SYNCPATs.
(2) t
RNM
represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
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