Datasheet

SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
SERIALIZER SWITCHING CHARACTERISTICS
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TLH(L)
LVDS low-to-high transition time R
L
= 27 Ω, C
L
= 10 pF to GND, See 0.2 0.4 ns
Figure 6
t
LTHL(L)
LVDS high-to-low transition time 0.25 0.4 ns
t
su(DI)
DIN0−DIN9 setup to TCLK 0.5 ns
See Figure 9
t
su(DI)
DIN0−DIN9 hold from TCLK 4 ns
t
d(HZ)
DO± high-to-high impedance state 2.5 5
delay
t
d(LZ)
DO± low-to-high impedance state 2.5 5
delay
R
L
= 27 Ω, C
L
= 10 pF to GND, See
ns
Figure 10
t
d(ZH)
DO± high-to-high impedance 5 10
state-to-high delay
t
d(ZL)
DO± high-to-high impedance 6.5 10
state-to-low delay
t
w(SPW)
SYNC pulse duration 6×t
TCP
ns
See Figure 12
t
(PLD)
Serializer PLL lock time 1026×t
TCP
ns
t
d(S)
Serializer delay See Figure 13 t
TCP
+1 t
TCP
+2 t
TCP
+3 ns
230
t
DJIT
Deterministic jitter RL = 27 Ω, C
L
= 10 pF to GND ps
150
t
RJIT
Random jitter RL = 27 Ω, C
L
= 10 pF to GND 10 19 ps (RMS)
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
RFCP
REFCLK period 15.15 T 100 ns
t
RFDC
REFCLK duty cycle 30% 50% 70%
t
t(RF)
REFCLK transition time 3 6 ns
Frequency tolerance -100 +100 ppm
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