Datasheet

0
100
200
300
400
500
600
700
800
900
1000
0 20 40 60 80 100 120 140
Termination(RL)- W
V IN-mV
OD
V
OD
SN65LV1023A
SN65LV1224B
www.ti.com SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
Figure 2. Typical V
OD
Curve
SERIALIZER TIMING REQUIREMENTS FOR TCLK
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TCP
Transmit clock period 15.15 T 100 ns
t
TCIH
Transmit clock high time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit clock low time 0.4T 0.5T 0.6T ns
t
t(CLK)
TCLK input transition time 3 6 ns
t
JIT
TCLK input jitter See Figure 19 150 ps (RMS)
Frequency tolerance -100 +100 ppm
Copyright © 2004–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65LV1023A SN65LV1224B