Datasheet

SYNC1
SYNC2
DEN
A+
A−
PLL
10
LVDS
Timing /
Control
Input Latch
Parallel-to-Serial
TCLK_R/F
D
IN
Y+
Y−
PLL
Timing /
Control
Output Latch
Serial-to-Parallel
Clock
Recovery
10
D
OUT
REN
REFCLK
LOCK
RCLK_R/F
RCLK
(10 MHz to
66 MHz)
TCLK
(10 MHz to
66 MHz)
SN65LV1224BSN65LV1023A
SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
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Product Folder Link(s): SN65LV1023A SN65LV1224B