Datasheet

R
L
D
O
+
D
O
−
10
D
IN
Parallel-to-Serial
> TCLK
V
OD
= (D
O
+) − (D
O
−)
Differential Output Signal Is Shown as (D
O
+) − (D
O
−)
3.0 V
V
DD
PWRDNB
SN65LV1023A
SN65LV1224B
www.ti.com SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
Figure 20. V
OD
Diagram
DEVICE STARTUP PROCEDURE
It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a
logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 21.
Figure 21. Device Startup
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Product Folder Link(s): SN65LV1023A SN65LV1224B