Datasheet

R
OUT
[9:0]
REFCLK
PWRDN
0.8 V
DATA
Not Important
SYNC Patterns
R
I
±
LOCK
3-State
3-State3-State
RCLK
3-State3-State
SYNC Symbol or D
IN
[9:0]
REN
t
(DSR2)
V
CC
3.6 V
3 V
0 V
1.2 V
1 V
t
d(ZH)
or t
d(ZL)
t
d(HZ)
or t
d(LZ)
t
DJIT
t
SW
: Setup and Hold Time (Internal Data Sampling Window)
t
DJIT
: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
t
RNM
: Receiver Noise Margin Time
V
TH
R
I
±
V
TL
1.2 V
1 V
t
DJIT
t
RNM
t
RNM
t
SW
Ideal Sampling Position
SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
Figure 18. Deserializer PLL Lock Time From SyncPAT
Figure 19. Receiver LVDS Input Skew Margin
18 Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65LV1023A SN65LV1224B