Datasheet

R
OUT
[9:0]
REFCLK
2 V
PWRDN
0.8 V
t
d(ZHL)
DATA
Not Important
3-State
SYNC Patterns
1.5 V
R
I
±
LOCK
3-State
3-State3-State
RCLK
3-State3-State
SYNC Symbol or D
IN
[9:0]
RCLK_R/F = Low
REN
t
(DSR1)
t
d(ZH)
or t
d(ZL)
t
d(HZ)
or t
d(LZ)
SN65LV1023A
SN65LV1224B
www.ti.com SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
Figure 17. Deserializer PLL Lock Times and PWRDN 3-State Delays
Copyright © 2004–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN65LV1023A SN65LV1224B