Datasheet

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SERIALIZER SWITCHING CHARACTERISTICS
t
TCP
2
 3
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
DESERIALIZER SWITCHING CHARACTERISTICS
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TLH(L)
LVDS low-to-high transition time 0.2 1
R
L
= 27 Ω , C
L
= 10 pF to GND, See
Figure 4
t
THL(L)
LVDS high-to-low transition time 0.25 1
t
su(DI)
D
IN0
-D
IN9
setup to TCLK 1 0
R
L
= 27 Ω , C
L
= 10 pF to GND, See
Figure 7
t
h(D)
D
IN0
-D
IN9
hold from TCLK 6.5 4.5
DO± high-to-high impedance
t
d(HZ)
2.5 5
state delay
DO± low-to-high impedance state
t
d(LZ)
2.5 5
delay
R
L
= 27 Ω , C
L
= 10 pF to GND, See
Figure 8
ns
DO± high-impedance
t
d(ZH)
2.5 10
state-to-high delay
DO± high-impedance state-to-low
t
d(ZL)
2.7 10
delay
t
w(SP)
SYNC pulse duration 6×t
TCP
R
L
= 27 Ω , See Figure 9
andFigure 10
t
PLD
Serializer PLL lock time 1026×t
TCP
t
d(S)
Serializer delay R
L
= 27 Ω , See Figure 11
t
(BIT)
Bus LVDS bit width R
L
= 27 Ω , C
L
= 10 pF to GND t
CLK
/12
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
RFCP
REFCLK period 25 T 100 ns
t
RFDC
REFCLK duty cycle 40% 50% 60%
t
t(RF)
REFCLK transition time 3 6 ns
Frequency tolerance -100 +100 ppm
over recommended operating supply and temperature ranges (unless otherwise specified)
TEST
PARAMETER PIN/FREQ MIN TYP MAX UNIT
CONDITIONS
t
(RCP)
= t
(TCP)
t
RCP
Receiver out clock period RCLK 25 100
See Figure 11
CMOS/TTL low-to-high transition
t
TLH(C)
0.7 2.5
R
OUT0
-
time
C
L
=15 pF,
R
OUT9
, LOC
ns
See Figure 5
CMOS/TTL high-to-low transition
K, RCLK
t
THL(C)
1.1 2.5
time
10 MHz 2×t
RCP
+ 9 2.833×t
RCP
+ 14
Room temperature,
t
d(D)
Deserializer delay, See Figure 12
3.3 V
40 MHz 2×t
RCP
+ 6 2.833×t
RCP
+ 10
t
su(ROS)
R
OUT0
-R
OUT9
setup data to RCLK 0.4×t
RCP
0.5×t
RCP
ns
t
(ROH)
R
OUT0
-R
OUT9
hold data to RCLK See Figure 13 RCLK -0.4×t
RCP
-0.5×t
RCP
t
(RDC)
RCLK duty cycle 40% 50% 60%
High-to-high impedance state
t
d(HZ)
6.7 8
delay
Low-to-high impedance state
t
d(LZ)
4.6 8
R
OUT0
-
delay
See Figure 14 R
OUT9
, ns
High-impedance state-to-high
LOCK
t
d(ZH)
5.5 8
delay
High-impedance state-to-low
t
d(ZL)
4.8 8
delay
9