Datasheet

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SERIALIZER TIMING REQUIREMENTS FOR TCLK
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
OZ
High-impedance output current PWRDN or REN = 0.8 V, V
OUT
= 0 V or V
CC
-10 ±1 10 µA
SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO-)
V
OD
Output differential voltage (DO+)-(DO-) 350 400 mV
∆ V
OD
Output differential voltage unbalance 35 mV
R
L
= 27 Ω , See Figure 18
V
OS
Offset voltage 1.1 1.2 1.3 V
∆ V
OS
Offset voltage unbalance 35 mV
I
OS
Output short circuit current D0 = 0 V, D
INx
= high, PWRDN and DEN = 2.4 V -10 -90 mA
I
OZ
High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or V
CC
-10 ±1 10 µA
I
OX
Power-off output current V
CC
= 0 V, DO = 0 V or V
CC
-20 ±1 20 µA
DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI-)
V
TH
Differential threshold high voltage V
CM
= 1.1 V 50 mV
V
TL
Differential threshold low voltage -50 mV
V
IN
= 2.4 V, V
CC
= 3.6 V or 0 V -10 ±1 15
I
IN
Input current µA
V
IN
= 0 V, V
CC
= 3.6 V or 0 V -10 ±0.05 10
SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 40 MHz 40 50
I
CCD
Serializer supply current, worst case R
L
= 27 Ω , See Figure 2 mA
f = 10 MHz 20 25
I
CCXD
Serializer supply current, power down PWRDN = 0.8 V 200 500 µA
DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)
f = 40 MHz 63 75
I
CCR
Deserializer supply current, worst case C
L
= 15 pF, See Figure 3 mA
f = 10 MHz 15 35
I
CCXR
Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V 0.36 1 mA
over recommended operating supply and temperature ranges (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
TCP
Transmit clock period 25 T 100 ns
t
TCIH
Transmit clock high time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit clock low time 0.4T 0.5T 0.6T ns
t
t(CLK)
TCLK input transition time See Figure 6 3 6 ns
t
JIT
TCLK input jitter 150 ps (RMS)
8