Datasheet

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SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
TERMINAL FUNCTIONS
PIN NAME DESCRIPTION
SERIALIZER
1, 2 SYNC1, SYNC2 LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted
high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after
completion of transmission of 1026 patterns SYNC continues to be asserted, then the transmission
continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern
transmission initiates.
3-12 D
IN0
-D
IN9
Parallel LVTTL data inputs
13 TCLK_R/ F LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data
strobe.
14 TCLK LVTTL-level reference clock input. The SN65LV1021 accepts a 10-MHz to 40-MHz clock. TCLK strobes
parallel data into the input latch and provides a reference frequency to the PLL.
15, 16 DGND Digital circuit ground
18, 20, 23, AGND Analog circuit ground (PLL and analog circuits)
25
17, 26 AV
CC
Analog circuit power supply (PLL and analog circuits)
19 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial
data output.
21 D
O
- Inverting LVDS differential output
22 D
O
+ Noninverting LVDS differential output
27, 28 DV
CC
Digital circuit power supply
24 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance
state, putting the device into a low-power mode.
DESERIALIZER
3 REFCLK LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency.
15-19, R
OUT0-
R
OUT9
Parallel LVTTL data outputs
24-28
2 RCLK_R/ F LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data
strobe.
9 RCLK LVTTL-level output recovered clock. Use RCLK to strobe R
OUTx
.
14, 20, 22 DGND Digital circuit ground
1, 12, 13 AGND Analog circuit ground (PLL and analog circuits)
4, 11 AV
CC
Analog circuit power supply (PLL and analog circuits)
8 REN LVTTL logic input. Low places R
OUT0
-R
OUT9
, LOCK, and RCLK in the high-impedance state.
5 R
I
+ Serial data input. Noninverting LVDS differential input
6 R
I
- Serial data input. Inverting LVDS differential input
10 LOCK LVTTL-level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge.
21, 23 DV
CC
Digital circuit power supply
7 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance
state, putting the device into a low-power mode.
6