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Start
Bit
Stop
Bit
D
IN0
Held Low and D
IN1
Held High
D
IN0
D
IN1
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
D
IN4
Held Low and D
IN5
Held High
D
IN4
D
IN5
Start
Bit
Stop
Bit
Start
Bit
Stop
Bit
D
IN8
Held Low and D
IN9
Held High
D
IN8
D
IN9
Start
Bit
Stop
Bit
DATA TRANSMISSION MODE
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
Figure 1. RMT Pattern Examples
After initialization and synchronization, the serializer accepts parallel data from inputs D
IN0
-D
IN9
. The serializer
uses the TCLK input to latch the incoming data. The TCLK_R/ F pin selects which edge the serializer uses to
strobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at D
IN0
-D
IN9
is ignored
regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.
After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±) at
12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 × 12 = 120 Mbps. Because
only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz,
the useful data rate is 10 × 12 = 120 Mbps. The data source, which provides TCLK, must be in the range of
10 MHz to 40 MHz.
The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.
The outputs transmit data when the enable pin (DEN) is high, PWRDN is high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the serializer output pins enter the high-impedance state.
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