Datasheet

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SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock
information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC
patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low.
When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the
deserializer LOCK output directly to SYNC1 or SYNC2.
• RANDOM-LOCK SYNCHRONIZATION: The deserializer can attain lock to a data stream without requiring
the serializer to send special SYNC patterns. This allows the SN65LV1212 to operate in open-loop
applications. Equally important is the deserializer's ability to support hot insertion into a running backplane. In
the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because
lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary
constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK
when the deserializer powers up.
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT);see Figure 1 for RMT examples. RMT occurs when more than one low-high transition takes
place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data
pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists.
Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern
changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock,
the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle.
The deserializer does not go into lock unitil it finds a unique four consecutive cycles of data boundary (stop/start
bits) at the same position.
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive
cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of
loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a
high-impedance state. The user's system should monitor the LOCK pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted.
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