Datasheet

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SYNC1
SYNC2
DEN
A+
A–
PLL
10
SN65LVDS1021
LVDS
Timing /
Control
Input Latch
Parallel-to-Serial
TCLK_R/F
D
IN
Y+
Y–
PLL
SN65LVDS1212
Timing /
Control
Output Latch
Serial-to-Parallel
Clock
Recovery
10
D
OUT
REN
REFCLK
LOCK
RCLK_R/F
RCLK
(10 MHz to
40 MHz)
TCLK
(10 MHz
to
40 MHz)
FUNCTIONAL DESCRIPTION
INITIALIZATION MODE
SYNCHRONIZATION MODE
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
The SN65LV1021 and SN65LV1212 are a 10-bit serializer/deserializer chipset designed to transmit data over
differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 40 MHz. The chipset
has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down
mode, and high-impedance mode. The following sections describe each state of operation.
Initialization of both devices must occur before data transmission can commence. Initialization refers to
synchronization of the serializer and deserializer PLLs to local clocks.
When V
CC
is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,
while on-chip power-on circuitry disables internal circuitry. When V
CC
reaches 2.45 V, the PLL in each device
begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an
external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs
remain in the high-impedance state, while the PLL locks to the TCLK.
The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be
accomplished in one of two ways:
• RAPID SYNCHRONIZATION: The serializer has the capability to send specific SYNC patterns consisting of
six ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the
deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC
patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid a SYNC1 or
SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.
2