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R
OUT
[9:0]
REFCLK
2 V
PWRDN
0.8 V
t
d(ZHL)
DATA
Not Important
3-State
SYNC Patterns
1.5 V
R
I
±
LOCK
3-State
3-State3-State
RCLK
3-State3-State
SYNC Symbol or D
IN
[9:0]
RCLK_R/F = Low
REN
t
d(HZ)
or t
d(LZ)
t
d(ZH)
or t
d(ZL)
t
DSR1
SN65LV1021
SN65LV1212
SLLS526G FEBRUARY 2002 REVISED DECEMBER 2005
Figure 15. Receiver LVDS Input Skew Margin
15