Datasheet

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R
I
Start
Bit
D
00
– D
09
SYMBOL N+2
Stop
Bit
1.2 V
1 V
Start
Bit
D
00
– D
09
SYMBOL N+1
Stop
Bit
Start
Bit
D
00
– D
09
SYMBOL N
Stop
Bit
RCLK
R
OUT
t
DD
R
OUT0
– R
OUT9
SYMBOL N–1 R
OUT0
– R
OUT9
SYMBOL N
R
OUT0
– R
OUT9
SYMBOL N+1
Timing for TCLK_R/F
= High
R
OUT
[9:0]
RCLK
RCLK_R/F = High
t
ROS
Data Valid
Before RCLK
1.5 V1.5 V
t
ROH
t
Low
t
High
RCLK
RCLK_R/F = Low
t
High
t
Low
Data Valid
After RCLK
7 V(LZ/ZL), Open (HZ/ZH)
REN
t
d(ZL)
t
d(LZ)
1.5 V1.5 V
V
OH
V
OL
V
OL
+ 0.5 V
V
OL
R
OUT
[9:0]
V
OH
t
d(ZH)
t
d(HZ)
500 Ω
450 Ω
50 Ω
Scope
V
OL
+ 0.5 V
V
OH
– 0.5 V
V
OH
– 0.5 V
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 12. Deserializer Delay
Figure 13. Deserializer Setup and Hold Times
Figure 14. Deserializer High-Impedance-State Test Circuit and Timing
14