Datasheet

www.ti.com
t
w(SP)
PWRDN
TCLK
REN
SYNC1
or
SYNC2
D
O
±
DATA SYNC Pattern
t
w(SP)
Min. Timing Met
TCLK
SYNC1
or
SYNC2
D
O
±
DATA
SYNC Pattern
D
O
Start
Bit
D
00
– D
09
SYMBOL N
Stop
Bit
Start
Bit D
00
– D
09
SYMBOL N–1
Stop
Bit
TCLK
D
IN
t
d(S)
D
IN0
– D
IN9
SYMBOL N D
IN0
– D
IN9
SYMBOL N+1
Timing for TCLK_R/F = High
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 10. SYNC Timing Delays
Figure 11. Serializer Delay
13