Datasheet

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13.5 Ω
D
O
+
D
O
–
Parasitic Package and
Trace Capacitance
DEN
t
d(HZ)
1.5 V1.5 V
3 V
0 V
50%50%
1.1 V
V
OH
D
O
±
V
OL
1.1 V
50%
50%
13.5 Ω
1.1 V
DEN
t
d(ZH)
t
d(ZL)
t
d(LZ)
D
O
±
TCLK
2 V
1026 Cycles
PWRDN
0.8 V
Output Active
t
(PLD)
t
d(ZH)
or t
d(ZL)
3-State 3-State
1026 Cycles
SYNC Pattern
DEN = High
t
w(SP)
SYNC
1.5 V 1.5 V
t
d(HZ)
or t
d(LZ)
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 8. Serializer High-Impedance-State Test Circuit and Timing
Figure 9. Serializer PLL Lock Time and PWRDN High-Impedance-State Delays
12