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80%
20%
80%
20%
t
TLH(L)
V
diff
R
L
10 pF
D
O
+
D
O
–
10 pF
V
diff
= (D
O
+) – (D
O
–)
t
THL(L)
80%
20%
80%
20%
CMOS/TTL Output
15 pF
Deserializer
t
TLH(C)
t
THL(L)
90%
10%
90%
10%
t
t(CLK)
TCLK
3 V
0 V
t
t(CLK)
D
IN
[9:0]
t
su(DI)
TCLK
t
h(DI)
For TCLK_R/F = Low
Setup Hold 1.5 V1.5 V
t
TCP
1.5 V 1.5 V 1.5 V
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
Figure 4. Serializer LVDS Output Load and Transition Times
Figure 5. Deserializer CMOS/TTL Output Load and Transition Times
Figure 6. Serializer Input Clock Transition Time
Figure 7. Serializer Setup/Hold Times
11