Datasheet

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RCLK
ODD R
OUT
EVEN R
OUT
TCLK
ODD D
IN
EVEN D
IN
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
DESERIALIZER SWITCHING CHARACTERISTICS (continued)
over recommended operating supply and temperature ranges (unless otherwise specified)
TEST
PARAMETER PIN/FREQ MIN TYP MAX UNIT
CONDITIONS
10 MHz (1024+26)t
RFCP
Deserializer PLL lock time from
t
(DSR1)
PWRDN(with SYNCPAT)
40 MHz (1024+26)t
RFCP
µs
See
10 MHz 0.7
Deserializer PLL lock time from
Figure 15 ,Figure 1
t
(DSR2)
SYNCPAT
40 MHz 0.2
6 , and Note
(1)
High-impedance state-to-high
t
d(ZHL)
LOCK 3 ns
delay (power up)
10 MHz 3680
See Figure 17 and
t
(RNM)
Deserializer noise margin ps
Note
(2)
40 MHz 1100
(1) t
(DSR1)
represents the time required for the deserializer to register that a lock has occurred upon power up or when leaving the
power-down mode. t
(DSR2)
represents the time required to register that a lock has occurred for the powered up and enabled deserializer
when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify
deserializer PLL performance t
DSR1
and t
DSR2
are specified with REFCLK active and stable and specific conditions of SYNCPATs.
(2) t
RNM
represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
TIMING DIAGRAMS AND TEST CIRCUITS
Figure 2. Worst-Case Serializer I
CC
Test Pattern
Figure 3. Worst-Case Deserializer I
CC
Test Pattern
10