Datasheet
RECEIVER ELECTRICAL CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
V
OC
V
OD
27
Ω
27
Ω
0 or 3 V
SN65LBC180A
SN75LBC180A
SLLS378D – MAY 2000 – REVISED APRIL 2009 ...............................................................................................................................................................
www.ti.com
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going input threshold voltage I
O
= – 8 mA 0.2 V
V
IT –
Negative-going input threshold voltage I
O
= 8 mA – 0.2 V
V
hys
Hysteresis voltage ( V
IT+
– V
IT –
) 50 mV
V
IK
Enable-input clamp voltage I
I
= – 18 mA – 1.5 – 0.8 V
V
OH
High-level output voltage V
ID
= 200 mV, I
OH
= – 8 mA 4 4.9 V
V
OL
Low-level output voltage V
ID
= – 200 mV, I
OL
= 8 mA 0.1 0.8 V
I
OZ
High-impedance-state output current V
O
= 0 V to V
CC
– 1 1 µ A
I
IH
High-level enable-input current V
IH
= 2.4 V – 100 µ A
I
IL
Low-level enable-input current V
IL
= 0.4 V – 100 µ A
V
I
= 12 V,
0.4 1
V
CC
= 5 V
V
I
= 12 V, 0.5 1
V
CC
= 0
I
I
Bus input current Other input at 0 V mA
V
I
= – 7 V,
– 0.8 – 0.4
V
CC
= 5 V
V
I
= – 7 V, – 0.8
– 0.3
V
CC
= 0
Receiver enabled and driver disabled 4.5 7.5
V
I
= 0 or V
CC
,
I
CC
Supply current Receiver disabled and driver disabled 0.5 1 mA
No load
Receiver enabled and driver enabled 8.5 15
(1) All typical values are at V
CC
= 5 V and T
A
= 25 ° C.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 7 13 20 ns
t
PHL
Propagation delay time, high-to-low-level output 7 13 20 ns
V
ID
= – 1.5 V to 1.5 V, See Figure 7
t
sk(p)
Pulse skew ( | t
PHL
– t
PLH
| ) 0.5 1.5 ns
t
r
Output signal rise time 2.1 3.3 ns
t
f
Output signal fall time See Figure 7 2.1 3.3 ns
t
PZH
Output enable time to high level 30 45 ns
t
PZL
Output enable time to low level 30 45 ns
C
L
= 10 pF, See Figure 8
t
PHZ
Output disable time from high level 20 40 ns
t
PLZ
Output disable time from low level 20 40 ns
Figure 1. Driver V
OD
and V
OC
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