Datasheet

SN65LBC174, SN75LBC174
QUADRUPLE LOW-POWER DIFFERENTIAL LINE DRIVERS
SLLS162D – JULY 1993 – REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IK
Input clamp voltage I
I
= –18 mA –1.5 V
|V |
Differential output voltage
‡
R
L
= 54
Ω
,
SN65LBC174 1.1 1.8 5
V
|V
OD
|
Differential output voltage
‡
R
L
= 54 ,
See Figure 1
SN75LBC174 1.5 1.8 5
V
|V
OD
|
Differential output voltage
‡
R
L
= 60
Ω
,
SN65LBC174 1.1 1.7 5
V
R
L
= 60 ,
See Figure 2
SN75LBC174 1.5 1.7 5
∆|V
OD
|
Change in magnitude of common-mode output voltage
§
R = 54 ,
See Figure 1
± 0.2 V
V
OC
Common-mode output voltage
R
L
= 54 Ω,
See Figure 1
3
V
V
OC
Common-mode output voltage
R
L
= 54 Ω,
See Figure 1
3
–1
V
∆|V
OC
|
Change in magnitude of common-mode output voltage
§
± 0.2 V
I
O
Output current with power off V
CC
= 0, V
O
= – 7 V to 12 V ± 100 µA
I
OZ
High-impedance-state output current V
O
= – 7 V to 12 V ± 100 µA
I
IH
High-level input current V
I
= 2.4 V –100 µA
I
IL
Low-level input current V
I
= 0.4 V –100 µA
I
OS
Short-circuit output current V
O
= –7 V to 12 V ± 250 mA
I
CC
Supply current (all drivers)
No load
Outputs enabled 7
mA
I
CC
Supply current (all drivers)
No load
Outputs disabled 1.5
mA
†
All typical values are at V
CC
= 5 V and T
A
= 25°C.
‡
The minimum V
OD
specification does not fully comply with EIA-485 at operating temperatures below 0°C. The lower output signal should be used
to determine the maximum signal transmission distance.
§
∆|V
OD
| and ∆|V
OC
| are the changes in magnitude of V
OD
and V
OC
, respectively, that occur when the input is changed from a high level to a low
level.
switching characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential output delay time
R
L
= 54 Ω, See Figure 3
2 11 20 ns
t
t(OD)
Differential output transition time
R
L
= 54 Ω, See Figure 3
10 15 25 ns
t
PZH
Output enable time to high level R
L
= 110 Ω, See Figure 3 20 30 ns
t
PZL
Output enable time to low level R
L
= 110 Ω, See Figure 5 21 30 ns
t
PHZ
Output disable time from high level R
L
= 110 Ω, See Figure 4 48 70 ns
t
PLZ
Output disable time from low level R
L
= 110 Ω, See Figure 5 21 30 ns