Datasheet

SN65LBC174A
SN75LBC174A
SLLS446F –OCTOBER 2000–REVISED OCTOBER 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input clamp voltage I
I
= -18 mA –1.5 –0.77 V
V
O
Open-circuit output voltage Y or Z, No load 0 V
CC
V
No load (open circuit) 3 V
CC
Steady-state differential output voltage
|V
OD(SS)
| R
L
= 54 Ω, See Figure 1 1 1.6 2.5 V
magnitude
(2)
With common-mode loading, See Figure 2 1 1.6 2.5
Change in steady-state differential
ΔV
OD(SS)
See Figure 1 –0.1 0.1 V
output voltage between logic states
Steady-state common-mode output
V
OC(SS)
See Figure 3 2 2.4 2.8 V
voltage
Change in steady-state common-mode
ΔV
OC(SS)
See Figure 3 –0.02 0.02 V
output voltage between logic states
I
I
Input current A, EN –50 50 μA
V
I
= 0 V
I
OS
Short-circuit output current –200 200 mA
V
I
= V
CC
V
TEST
= -7 V to 12 V, See
Figure 7
I
OZ
High-impedance-state output current EN at 0 V –50 50
μA
I
O(OFF)
Output current with power off V
CC
= 0 V –10 10
All drivers enabled 23
I
CC
Supply current V
I
= 0 V or V
CC,
No load mA
All drivers disabled 1.5
A inputs 13 pF
C
IN
Input Capacitance
EN inputs 21 pF
(1) All typical values are at V
CC
= 5 V and 25°C.
(2) The minimum V
OD
may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the
possibly lower output signal into account in determining the maximum signal transmission distance.
SWITCHING CHARACTERISTICS
over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high level output 5.5 8 11 ns
t
PHL
Propagation delay time, high-to-low level output 5.5 8 11 ns
t
r
Differential output voltage rise time 3 7.5 11 ns
t
f
Differential output voltage fall time 3 7.5 11 ns
R
L
= 54 Ω, C
L
= 50 pF,
See Figure 4
0.6 2
t
sk(p)
Pulse skew |t
PLH
– t
PHL
| ns
0.6 2
t
sk(o)
Output skew
(1)
2 ns
t
sk(pp)
Part-to-part skew
(2)
3 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output 25 ns
See Figure 5
t
PHZ
Propagation delay time, high-level-output-to-high impedance 25 ns
t
PZL
Propagation delay time, high-impedance-to-low-level output 30 ns
See Figure 6
t
PLZ
Propagation delay time, low-level-output-to-high impedance 20 ns
(1) Output skew (t
sk(o)
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected
together.
(2) Part-to-part skew (t
sk(pp)
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices
when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical
packages and test circuits.
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