Datasheet

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    
SLLS163E − JULY 1993 − REVISED APRIL 2006
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OC
2
R
L
2
R
L
V
OD2
Figure 1. Differential and Common-Mode Output Voltages
R2 = 375 Ω
V
OD
R
L
= 60 Ω
V
test
V
test
0 V or 3 V
A
R1 = 375 Ω
Y
Z
−7 V < V
test
< 12 V
G at 5 V
or
G
at 0 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t
r
≤ 5 ns,
t
f
≤ 5 ns, Z
O
= 50 Ω.
B. C
L
includes probe and stray capacitance.
Figure 2. Driver V
OD
Test Circuit
VOLTAGE WAVEFORMS
50%
t
t(OD)
t
d(OD)
10%
t
t(OD)
≈ 2.5 V
≈ − 2.5 V
90%
50%
Output
t
d(OD)
0 V
3 V
Input
TEST CIRCUIT
Output
C
L
= 50 pF
(see Note B)
R
L
= 54 Ω
50 Ω
1.5 V 1.5 V
3 V
Input
Generator
(see Note A)
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t
r
≤ 5 ns,
t
f
≤ 5 ns, Z
O
= 50 Ω.
B. C
L
includes probe and stray capacitance.
Figure 3. Driver Differential-Output Test Circuit and Delay and Transition-Time Waveforms