Datasheet

ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
SN65HVS885
www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009
over full-range of recommended operating conditions (unless otherwise noted)
all voltages measured against device ground, see Figure 9
PARAMETER TERMINAL TEST CONDITIONS MIN TYP MAX UNIT
FIELD INPUTS
V
TH – (IP)
Low-level device input threshold voltage 4.0 4.3 V
V
TH+(IP)
High-level device input threshold voltage IP0 – IP7 R
LIM
= 25 k Ω 5.2 5.5 V
V
HYS(IP)
Device input hysteresis 0.9 V
V
TH – (IN)
Low-level field input threshold voltage 6 8.4 V
4.5 V < V
CC
< 5.5 V,
measured at
V
TH+(IN)
High-level field input threshold voltage R
IN
= 1.2 k Ω ± 5%, 9.4 10 V
field side of R
IN
R
LIM
= 25 k Ω , T
A
≤ 125 ° C
V
HYS(IN)
Field input hysteresis 1 V
3 V < V
IPx
< 6 V,
R
IP
Input resistance IP0 – IP7 0.2 0.63 1.1 k Ω
R
LIM
= 25 k Ω
I
IP-LIM
Input current limit IP0 – IP7 R
LIM
= 25 k Ω 3.15 3.6 4 mA
DB0 = open, DB1 = GND 0
t
DB
Debounce times of input channels IP0 – IP7 DB0 = GND, DB1 = open 1 ms
DB0 = DB1 = open 3
I
RE-on
RE on-state current RE0 – RE7 R
LIM
= 25 k Ω , RE
X
= GND 2.8 3.15 3.5 mA
DEVICE SUPPLY
IP0 to IP7 = 24V, RE
X
= GND,
I
CC(VCC)
Supply current V
CC
6.5 10 mA
All logic inputs open
LOGIC INPUTS AND OUTPUTS
V
OL
Logic low-level output voltage I
OL
= 20 µ A 0.4 V
SOP, HOT
V
OH
Logic high-level output voltage I
OH
= – 20 µ A 4 V
DB0, DB1, SIP,
I
IL
Logic input leakage current – 50 50 µ A
LD, CE, CLK
T
OVER
Over-temperature indication 150 ° C
T
SHDN
Shutdown temperature 170 ° C
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
W1
CLK pulse width See Figure 6 4 ns
t
W2
LD pulse width See Figure 4 6 ns
t
SU1
SIP to CLK setup time See Figure 7 4 ns
t
H1
SIP to CLK hold time See Figure 7 2 ns
t
SU2
Falling edge to rising edge ( CE to CLK) setup time See Figure 8 4 ns
t
REC
LD to CLK recovery time See Figure 5 2 ns
f
CLK
Clock pulse frequency See Figure 6 DC 100 MHz
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH1
, t
PHL1
CLK to SOP C
L
= 15 pF, see Figure 6 10 ns
t
PLH2
, t
PHL2
LD to SOP C
L
= 15 pF, see Figure 4 14 ns
t
r
, t
f
Rise and fall times C
L
= 15 pF, see Figure 6 6 ns
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