Datasheet

IP6 IP5 IP4 IP3 IP2 IP1 IP0 SIPIP7don’t care
CLK
CE
LD
SIP
PIP0–PIP6
PIP7
SOP
inhibit
high
Serial shift
Cascading for High Channel Count Input Modules
4 xSN65 HVS 885
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
ISO7241
HOST
CONTROLLER
LOAD
STE
SCLK
SOMI
SERIALIZER
IP0 IP7
SIP
LD
CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
LD
CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
LD
CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
LD
CE
CLK
SOP
SN65HVS885
www.ti.com ............................................................................................................................................................................................... SLAS638 – JANUARY 2009
Figure 17. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Designing high-channel count modules require cascading multiple SN65HVS885 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
Figure 18. Cascading Four SN65HVS885 for a 32-Channel Input Module
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Product Folder Link(s): SN65HVS885