Datasheet
APPLICATION INFORMATION
System-Level EMC
V
CC
R
IN
C
IN
IP0 – IP 7
GND
SN65HVS885
INx
0 V
FE
C
S
5 V
1mF
R
IN
C
IN
C
S
1.2 kW, 1/4 WMELFResistor
220 nF, 60 VCeramicCapacitor
4.7 nF, 2 kVCeramicCapacitor
Input Channel Switching Characteristics
30
25
20
15
10
5
0
–3
5
10 15
30
25
20
15
10
5
0
-–3
5
10 15
I (mA)
IN
V (V)
IN
V (V)
IN
V
(V)
IN
I (mA)
IN
I (mA)
IN
30
25
20
15
10
5
0
–3
5
10 1520 25 30
Type1
Type2 Type3
OFF
ON
OFFOFF
ONON
0
00
SN65HVS885
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............................................................................................................................................................................................... SLAS638 – JANUARY 2009
The SN65HVS885 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards.
In addition to the device internal ESD structures, external protection circuitry shown in Figure 13 , can be used to
absorb as much energy from burst- and surge-transients as possible.
Figure 13. Typical EMC Protection Circuitry for Supply and Signal Inputs
The input stage of the HVS885 is so designed, that for an input resistor R
IN
= 1.2 k Ω the trip point for signaling
an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC61131-2 Type 1
and Type 3 switches.
Figure 14. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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