Datasheet

IP6 IP5 IP4 IP3 IP2 IP1 IP0 SIPIP7don’t care
CLK
CE
LD
SIP
PIP0–PIP6
PIP7
SOP
inhibit
high
Serial shift
Cascading for High Channel Count Input Modules
4 SN65HVS882X
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
ISO7241
HOST
CONTROLLER
LOAD
STE
SCLK
SOMI
SERIALIZER SERIALIZER SERIALIZER SERIALIZER
SIP
LD
CE
CLK
SOP
SIP
LD
CE
CLK
SOP
SIP
LD
CE
CLK
SOP
IP0
IP7
IP0
IP7
IP0
IP7
IP0
IP7
SIP
LD
CE
CLK
SOP
SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
Figure 19. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Designing high-channel count modules requires cascading multiple SN65HVS882 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
Figure 20. Cascading Four SN65HVS882 for a 32-Channel Input Module
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Product Folder Link(s): SN65HVS882