Datasheet

R
IN
R
IN
R
IN
C
IN
C
IN
C
IN
C
IN
R
IN
RE0
RE0
IP0
IP0
RE1
RE1
IP1
IP1
Digital Interface Timing
IP0
IP7
SN65HVS882
ISO7241
SERIALIZER
HOST
CONTROLLER
SIP
LD
CE
CLK
SOP
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
LOAD
STE
SCLK
SOMI
VREG
5V
V
CC
SN65HVS882
SLAS601 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
Figure 17. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
The digital interface of the SN65HVS882 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard microcontrollers.
Figure 18. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift
register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at
the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data
is clocked at the rising edge of CLK. Thus after eight consecutive clock cycles all field input data have been
clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP.
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