Datasheet

REF
R
LIM
IPx
REx
GND
5V
Shift Register
CP
D Q
SR
SOP
SIP
LD
PIP
1
PIP
2
PIP
3
PIP
4
PIP
5
PIP
6
PIP
7
PIP
0
CLK
CE
Logic
CP
D Q
SR
CP
D Q
SR
CP
D Q
SR
CP
D Q
SR
CP
D Q
SR
CP
D Q
SR
CP
D Q
SR
SN65HVS882
www.ti.com ........................................................................................................................................................................................................ SLAS601 – MAY 2008
Figure 13. Equivalent Input Diagram
The conversion from parallel input to serial output data is performed by an eight-channel serial-in parallel-out
shift register. Parallel-in access is provided by the internal inputs, PIP0 – PIP7, that are enabled by a low level at
the load input ( LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register
also provides a clock-enable function.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock
enable ( CE) input is held low. Parallel loading is inhibited when LD is held high. The parallel inputs to the register
are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.
Figure 14. Shift Register Logic Structure
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