Datasheet

IP6 IP 5 IP4 IP3 IP 2 IP1 IP 0IP7
high
HOT UVO PAR SIP
don’tcare
CLK
CE
LD
SIP
PAR - PIP 6
PIP 7
SOP
inhibit
Serialshift
Cascading for High Channel Count Input Modules
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
HOST
CONTROLLER
LOAD
STE
SCLK
SOMI
SERIALIZER
IP0 IP7
SIP
/LD
/CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
/LD
/CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
/LD
/CE
CLK
SOP
SERIALIZER
IP0 IP7
SIP
/LD
/CE
CLK
SOP
4xSN65HVS881
ISO7241
SN65HVS881
www.ti.com ................................................................................................................................................................................................... SLAS642 – MARCH 2009
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Designing high-channel count modules requires cascading multiple SN65HVS881 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
Figure 22. Cascading Four SN65HVS881 for a 32-Channel Input Module
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Product Folder Link(s): SN65HVS881