Datasheet

R
IN
C
IN
RE 0
IP 0
R
IN
C
IN
RE1
IP 1
R
IN
C
IN
RE0
IP0
R
IN
C
IN
RE1
IP1
Digital Interface Timing
SERIALIZER
IP0
IP7
SN65HVS881
SIP
LD
CE
CLK
SOP
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
ISO7241
HOST
CONTROLLER
LOAD
STE
SCLK
SOMI
SN65HVS881
SLAS642 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com
Figure 19. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
The digital interface of the SN65HVS881 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard microcontrollers.
Figure 20. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, /LD, the information of the field inputs and the diagnostic bits are latched into
the shift register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A
low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial
output, SOP. Data is clocked at the rising edge of CLK. Thus after eleven consecutive clock cycles all data have
been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output,
SOP.
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Product Folder Link(s): SN65HVS881