Datasheet

APPLICATION INFORMATION
System-Level EMC
V24
D
S
C
S
R
1
D
1
C
1
R
IN
C
IN
IP0 – IP7
FGND
C
S
V
SUP
= 24V
IPx
0 V
FE
D
2
FGND
0 V
FE
R
1
D
1
C
1
R
IN
C
IN
C
S
D
S
D
2
33 V – 36 VfastZenerDiode, Z2SMB36
10 µF, 60 VCeramicCapacitor
1.2 kW, 1/4 WMELFResistor
22 nF, 60 VCeramicCapacitor
4.7 nF, 2 kVPolypropyleneCapacitor
39V TransientVoltageSuppressor: SM15T39CA
SuperRectifier: BYM10-1000, or
GeneralPurposerectifier: 1N4007
56 W, 1/3 WMELFResistor
SN65HVS881
Input Channel Switching for IEC61131-2 PLC Applications
30
25
20
15
10
5
0
-3
5 10 15
V
IN
/ V
I
IN
/ mA
Type 1
OFF
ON
30
25
20
15
10
5
0
-3
5 10 15
V
IN
/ V
I
IN
/ mA
Type 3
OFF
ON
30
25
20
15
10
5
0
-3
5 10 15
V
IN
/ V
I
IN
/ mA
20 25 30
Type 2
OFF
ON
SN65HVS881
www.ti.com ................................................................................................................................................................................................... SLAS642 – MARCH 2009
The SN65HVS881 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the
device internal ESD structures, external protection circuitry, as shown in Figure 17 , can be used to absorb as
much energy from burst- and surge-transients as possible.
Figure 17. Typical EMC Protection Circuitry for Supply and Signal Inputs
The input stage of the SN65HVS881 is designed so that with a 24-V supply on V
CC
and an input resistor R
IN
=
1.2 k Ω , the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching
requirements of IEC61131-2 type-1 and type-3 switches.
Figure 18. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a type-2 switch application two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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