Datasheet

Voltage Regulator
>
I
C
L-MIN
L
1 mA
1 µF
Temperature Sensor
Parity Generator
SN65HVS881
SLAS642 – MARCH 2009 ................................................................................................................................................................................................... www.ti.com
Table 2. Function Table
INPUTS
FUNCTION
LD CLK CE
L X X Parallel load
H X H No change
H ↑ L Shift
(1)
(1) Shift = content of each internal register shifts towards serial outputs.
Data at SIP is shifted into first register.
The on-chip linear voltage regulator provides a 5V supply to the internal- and external-circuitry, such as digital
isolators, with an output drive capability of 50 mA and a typical current limit of 115 mA. The regulator accepts
input voltages from 30V down to 10V. Because the regulator output is intended to supply external digital isolator
circuits proper output voltage decoupling is required. For best results connect a 1 µ F and a 0.1 µ F ceramic
capacitor as close as possible to the 5VOP-output. For longer traces between the SN65HVS881 and isolators of
the ISO72xx family use additional 0.1 µ F and 10pF capacitors next to the isolator supply pins. Make sure,
however, that the total load capacitance does not exceed 4.7 µ F.
For good stability the voltage regulator requires a minimum load current, I
L-MIN
. Ensure that under any operating
condition the ratio of the minimum load current in mA to the total load capacitance in µ F is larger than 1:
An on-chip temperature sensor monitors the device temperature and signals a fault condition if the internal
temperature reaches 150 ° C. If the internal temperature exceeds this trip point, the HOT output switches to an
active low state. If the internal temperature continues to rise, passing a second trip point at 170 ° C, all device
outputs are put in a high-impedance state.
A special condition occurs, however, when the chip temperature exceeds the second temperature trip point due
to an output short. Then the output buffer becomes 3-state, thus separating the buffer from the external circuitry.
An internal 100-k Ω pull-down resistor, connecting the HOT pin to ground, is used as a cooling down resistor,
which continues to provide a logic low level to the external circuitry.
A parity bit is generated when one or more of the following conditions occur:
• a change in input status
• a change in Undervoltage status
• a change in Overtemperature status
Upon the application of a load pulse the input status (IP0 – IP7) and the diagnostic bits (HOT, UVO, and PAR) are
loaded parallel into the serializer assuming the following format:
Bit 11 Bit 1
PAR UVO HOT PIP0 PIP1 PIP2 PIP3 PIP4 PIP5 PIP6 PIP7
Figure 16. Sequence of Status Bits in Serializer
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