Datasheet

IP6 IP 5 IP 4 IP3 IP2 IP 1 IP0 SIPIP7don’t care
CLK
CE
LD
SIP
PIP0–PIP6
PIP7
SOP
inhibit
high
Serial shift
Cascading for High Channel Count Input Modules
4 SN65HVS880X
OUTA
OUTB
OUTC
IND
INA
INB
INC
OUTD
ISO7241
HOST
CONTROLLER
LOAD
STE
SCLK
SOMI
SERIALIZER SERIALIZER SERIALIZER SERIALIZER
SIP
LD
CE
CLK
SOP
SIP
LD
CE
CLK
SOP
SIP
LD
CE
CLK
SOP
IP0
IP7
IP0
IP7
IP0
IP7
IP0
IP7
SIP
LD
CE
CLK
SOP
SN65HVS880
SLAS592C MARCH 2008 REVISED NOVEMBER 2008 ...............................................................................................................................................
www.ti.com
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Designing high-channel count modules require cascading multiple SN65HVS880 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
Figure 22. Cascading Four SN65HVS880 for a 32-Channel Input Module
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Product Folder Link(s): SN65HVS880