Datasheet

DESCRIPTION (CONTINUED)
STB
Bus V
Diff
RXD
Standby Mode, STB = High
<t
BUS
<t
BUS
<t
BUS
t
BUS
t
BUS
STB
RXD
Bus V
Diff
Standby Mode, STB = High
<t
Clear
<t
BUS
t
BUS
t
BUS
t
Clear
t
BUS
t
BUS
SN65HVDA540
SN65HVDA541
SLLS981 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The SN65HVDA540/SN65HVDA541 has an I/O supply voltage input pin (V
IO
, pin 5) to ratiometrically level shift
the digital logic input and output levels with repsect to V
IO
for compatibility with protocol controllers having I/O
supply voltages between 3 V and 5.25 V. The V
IO
supply also powers the low-power bus monitor and wake-up
receiver of the SN65HVDA541 allowing the 5 V (V
CC
) supply to be switched off for additional power savings at
the system level during standby mode for either the SN65HVDA540 or SN65HVDA541. The 5 V (V
CC
) supply
needs to be reactivated by the local protocol controller at any time to resume high speed operation if it has been
turned off for low-power standby operation. Both of the supply pins have undervoltage detection which place the
device in standby mode to protect the bus during an undervoltage event on either the V
CC
or V
IO
supply pins. If
V
IO
is undervoltage the RXD pin is 3-statedn and the device does not pass any wake-up signals from the bus to
the RXD pin.
STB (pin 8) provides for two different modes of operation: normal mode or low-power standby mode. The normal
mode of operation is selected by applying a low logic level to STB. If a high logic level is applied to STB, the
device enters standby mode (see Figure 1 and Figure 2 ). In standby mode, the SN65HVDA541 provides a
wake-up receiver and monitor that remains active supplied via the V
IO
pin so that V
CC
may be removed allowing
a system level reduction in standby current. A dominant signal on the bus longer than the wake-up signal time
(t
BUS
) is passed to the receiver output (RXD, pin 4) by the wake-up bus monitor circuit. The local protocol
controller may then return the device to normal mode when the system needs to transmit or fully monitor the
messages on the bus. If the bus has a fault condition where it is stuck dominant while the SN65HVDA541 is
placed into standby mode, the device locks out the wake-up receiver output to RXD until the fault has been
removed to prevent false wake-up signals in the system. Because the SN65HVDA540 does not have a
low-power bus monitor and wake-up receiver, it provides a logic high output (recessive) on RXD while in standby
mode.
Figure 1. SN65HVDA541 Entering Standby Mode With Bus Recessive Condition
Figure 2. SN65HVDA541 Entering Standby Mode With Bus Dominant Condition
A dominant time-out circuit prevents the driver from blocking network communication in event of a hardware or
software failure. The dominant time out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is
seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is reset by the next
rising edge on TXD.
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