Datasheet

LIN Bus
Signal
DOMINANT
RECESSIVE
D = 0.5
Thresholds:
Worst case 1
Thresholds:
Worst case 2
t
Bit
t
Bit
V
sup
TH
Rec(max)
TH
Dom(max)
TH
Rec(min)
TH
Dom(min)
TXD (Input)
t
Bus_dom(max)
t
Bus_dom(min)
t
Bus_rec(max)
t
Bus_rec(min)
D = t
Bus_rec(min)
/(2 x t
Bit
)
D = t
Bus_rec(max)
/(2 x t
Bit
)
RXD
D2 (20 kbps) and
D4 (10 kbps) case
RXD
D1 (20 kbps) and
D3 (10 kbps) case
50% 50%
LIN Bus
RXD
0.4 V
SUP
0.6 V
SUP
V
SUP
t
rx_pdf
t
rx_pdr
SN65HVDA195-Q1
SLLS961A –JULY 2009–REVISED OCTOBER 2009 www.ti.com
TIMING DIAGRAMS
Figure 5. Definition of Bus Timing Parameters
Figure 6. Propagation Delay
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