Datasheet

SN65HVDA1050A-Q1
SLLS994A –FEBRUARY 2010–REVISED DECEMBER 2010 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, T
A
= –40 to 125°C (unless otherwise noted)
NO. PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
-20 V ≤ V
CANH
≤ 32 V, CANL
6.21 open, –15 15
TXD = high, See Figure 12
Short-circuit steady-state output current,
I
OS(ss)
mA
Recessive
-20 V ≤ V
CANL
≤ 32 V, CANH
6.22 open, –15 15
TXD = high, See Figure 12
6.23 C
O
Output capacitance See receiver input capacitance
Driver Switching Characteristics
Propagation delay time, low-to-high level
7.1 t
PLH
S = 0 V, See Figure 5 25 65 120 ns
output
Propagation delay time, high-to-low level
7.2 t
PHL
S = 0 V, See Figure 5 25 45 120 ns
output
7.3 t
r
Differential output signal rise time S = 0 V, See Figure 5 25 ns
7.4 t
f
Differential output signal fall time S = 0 V, See Figure 5 50 ns
Enable time from silent mode to normal
7.5 t
en
See Figure 8 1 µs
mode and transmission of dominant
7.6 t
(dom)
Dominant time out
(2)
↓V
I
, See Figure 11 300 450 700 µs
Receiver
8.1 V
IT+
Positive-going input threshold voltage S = 0 V, See Table 4 800 900 mV
8.2 V
IT–
Negative-going input threshold voltage S = 0 V, See Table 4 500 650 mV
8.3 V
hys
Hysteresis voltage (V
IT+
– V
IT–
) 100 125 mV
8.4 V
OH
High-level output voltage I
O
= –2 mA, See Figure 7 4 4.6 V
8.5 V
OL
Low-level output voltage I
O
= 2 mA, See Figure 7 0.2 0.4 V
CANH or CANL = 5 V,
Power-off bus input current (unpowered
8.6 I
I(off)
Other pin at 0 V, 165 250 µA
bus leakage current)
V
CC
at 0 V, TXD at 0 V
8.7 I
O(off)
Power-off RXD leakage current V
CC
at 0 V, RXD at 5 V 20 µA
Input capacitance to ground (CANH or TXD at 3 V,
8.8 C
I
13 pF
CANL) V
I
= 0.4 sin (4E6pt) + 2.5 V
8.9 C
ID
Differential input capacitance TXD at 3 V, V
I
= 0.4 sin (4E6pt) 6 pF
8.10 R
ID
Differential input resistance TXD at 3 V, S = 0 V 30 80 kΩ
8.11 R
IN
Input resistance (CANH or CANL) TXD at 3 V, S = 0 V 15 30 40 kΩ
Input resistance matching
8.12 R
I(m)
V
(CANH)
= V
(CANL)
–3 0 3 %
[1 – (R
IN (CANH)
/ R
IN (CANL)
)] × 100%
Receiver Switching Characteristics
Propagation delay time, low-to-high-level
9.1 t
PLH
S = 0 V or V
CC
, See Figure 7 60 100 130 ns
output
Propagation delay time, high-to-low-level
9.2 t
PHL
S = 0 V or V
CC
, See Figure 7 45 70 130 ns
output
9.3 t
r
Output signal rise time S = 0 V or V
CC
, See Figure 7 8 ns
9.4 t
f
Output signal fall time S = 0 V or V
CC
, See Figure 7 8 ns
(2) The TXD dominant time out (t(dom)) will disable the driver of the transceiver once the TXD has been dominant longer than t
(dom)
which
will release the bus lines to recessive preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults locking the bus dominant it will limit
the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case
where five successive dominant bits are followed immediately by an error frame. This along with the t
(dom)
minimum will limit the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t
(dom)
= 11 bits / 300µs = 37 kbps.
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