Datasheet

GND

SN65HVDA1050A

CANL

CANH

SPLIT (V )

REF

V = ½V in normal mode,

floating in other modes

SPLIT CC

SN65HVDA1050A-Q1

www.ti.com

SLLS994A –FEBRUARY 2010–REVISED DECEMBER 2010

Application Hints

Using With 3.3-V Microcontrollers

The input level threshold for the digital input pins of this device are 3.3V compatible, however a few application

considerations must be taken if using this device with 3.3-V microcontrollers. The TXD input pin has an internal

pullup source to V

. Some microcontroller vendors recommend using an open-drain configuration on their I/O

pins in this case even though the pullup limits the current. As such care must be taken at the application level

that TXD has sufficient pull up to meet system timing requirements for CAN. The internal pull up on TXD

especially may not be sufficient to overcome the parasitic capacitances and allow for adequate CAN timing; thus,

an additional external pullup may be required. Care should also be taken with the RXD pin of the microcontroller

as this device's RXD output drives the full V

range (5 V). If the microcontroller RXD input pin is not 5-V

tolerant, this must be addressed at the application level. Other options include using a CAN transceiver from

Texas Instruments with I/O level adapting or a 3.3-V CAN transceiver.

Using SPLIT (V

REF

) With Split Termination

The SPLIT (V

REF

) pin voltage output provides 0.5 × V

in normal mode. This pin is specified for both the SPLIT

sink/source current condition and the V

REF

sink/source current condition. The circuit may be used by the

application to stabilized the common-mode voltage of the bus by connecting it to the center tap of split

termination for the CAN network (see Figure 13 and Figure 2). This pin provides a stabilizing recessive voltage

drive to offset leakage currents of un-powered transceivers or other bias imbalances that might bring the network

common mode voltage away from 0.5 × V

. Utilizing this feature in a CAN network improves electromagnetic

emissions behavior of the network by eliminating fluctuations in the bus common-mode voltage levels at the start

of message transmissions.

Figure 2. Split Pin Stabilization Circuitry and Application

Product Folder Link(s): SN65HVDA1050A-Q1